pulp-platform / axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
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AXI Adapter(s) for RISC-V Atomic Operations
RISC-V Debug Support for our PULP RISC-V Cores
Generic Register Interface (contains various adapters)
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
OpenTitan: Open source silicon root of trust
Pipelines the AXI path with FIFOs
SystemVerilog modules and classes commonly used for verification
[UNRELEASED] FP div/sqrt unit for transprecision
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
Common SystemVerilog components
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Simple single-port AXI memory interface
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication